The present invention relates to a power supply disconnection system for a semiconductor device, which has the function of controlling connection and disconnection between a plurality of power supplies in the semiconductor device and the function of preventing a surge breakdown after a package assembling process, such that the number of power supplies which apply a voltage in a wafer level burn-in (WLBI) process can be reduced.
In recent years, along with the advancement of functional synthesis in a system LSI device, a larger number of system LSI devices have incorporated analog circuits. Further, a separate power supply which is disconnected from the other power supplies is necessary for each analog circuit in order to avoid effects of noise, and the like. To this end, multi power supply design in LSI devices has been becoming mainstream.
In addition, a process technique whose resolution has been increasing is employed, and accordingly, the number of separate power supplies has been increasing such that, for example, the supply voltage of an internal circuit is different from that of an IO circuit.
Further, a micro-process technique is employed to reduce the chip area, and achievement of a large diameter wafer increases the number of chips obtained from the wafer. Shift from package burn-in (package BI) wherein the burn-in process is performed after package assemblage has been done to WLBI wherein a wafer is processed at once so that the cost is greatly reduced as compared with the package BI has been rapidly advancing.
In some power supply disconnection systems for conventional semiconductor devices, in general, a power supply disconnection cell is provided between power supplies.
FIG. 3 shows the above-described conventional semiconductor device. The semiconductor device of FIG. 3 includes a first analog circuit 100 and a second analog circuit 110. The first analog circuit 100 is connected to a first analog IO region 103 including a first analog VDD terminal 101 which supplies a VDD voltage and a first analog VSS terminal 102 which supplies a VSS voltage. The second analog circuit 110 is connected to a second analog IO region 113 including a second analog VDD terminal 111 which supplies a VDD voltage and a second analog VSS terminal 112 which supplies a VSS voltage. The semiconductor device of FIG. 3 further includes a power supply disconnection cell 200 for disconnecting the first analog IO region 103 and the second analog IO region 113.
The power supply disconnection cell 200 includes two protection transistors 201 and 202 between power supplies such that the gates of the protection transistors 201 and 202 are connected to the VSS power supply line. The transistor 201 is provided by a source-drain connection between the VDD power supply lines that exist between the analog IO regions 103 and 113. The transistor 202 is provided by a source-drain connection between the VSS power supply lines that exist between the analog IO regions 103 and 113. In the structure of FIG. 3, when an abnormal voltage which exceeds a rating is applied to a VSS terminal, the protection transistors 201 and 202 function such that electric charges are released through the source-drain. Thus, the transistors 201 and 202 serve to prevent a quality deterioration due to surge breakdown, or the like, in the analog IO regions 103 and 113.
Japanese Unexamined Patent Publication No. 05-291368 discloses a technique for achieving a reduction in the number of pads for probing in a WLBI process. The technique of Japanese Unexamined Patent Publication No. 05-291368 is that power supply potential lines are connected to each other through a transistor, and ground potential lines are connected to each other through a transistor. The transistor is controlled by a voltage input through a terminal for a voltage stress test which is connected to the gate of the transistor, and a short circuit is caused between power supply potential lines such that these lines are temporarily integrated, while another short circuit is caused between ground potential lines such that these lines are also temporarily integrated. The number of pads to be probed is reduced according to the number of short circuits, i.e., the number of short-circuited transistors.
In the above conventional technique, probes are placed on the pads for supplying the power supply voltage, inputting a control signal or input signal, and extracting a monitor output signal in the WLBI process. However, the number of electrically-connectable and probeable pads over one wafer is limited due to the flatness of the wafer, the probe pressure against the wafer, and the like. Because of this restriction, in a conventional semiconductor device, the number of probeable pads allocated to each chip is reduced as the number of chips obtained from one wafer increases. As a result, voltage application cannot be achieved in all of the separate power supplies in an LSI device of a multi power supply design, and WLBI cannot be employed in this device.
In the conventional technique disclosed in Japanese Unexamined Patent Publication No. 05-291368, means for reducing the number of terminals used in the WLBI process is to newly provide a transistor that can be short-circuited to temporarily integrate a plurality of power supply lines to which equal voltages are applied. However, this results in an increase in the chip area and causes an increase in cost.
Furthermore, since short-circuited transistors do not function as protection transistors, deterioration in quality may be caused due to a surge, or the like.